ASIC Design Verification Engineer

Amaris is an International Consulting group specialized in Technologies & Management, based in 27 countries throughout 32 subsidiaries. Amaris based its growth on human-sized teams and brings its customers a close-at-hand relationship and high added value projects.
Present on different projects for major accounts from all sectors of activity (industry, finance, telecoms, energy, public sector, transport…), our main fields of intervention are :
• Consulting & AMOA management
• Project management assistance and IT engineering
• Engineering and high technologies
• Biotechnologies and Pharmaceutical
Our growth is one of the best in the sector in Europe thanks to our teams’ quality of work and our customers’ satisfaction.
To accompany our development, we are searching for:



Your main responsibilities:
- Analyze & comprehend design specifications, industry standards, customer requirements and applications to establish verification requirements and scope of work.
- Develop verification plans outlining test strategy, environment, elements, test-cases and coverage goals to guarantee compliancy to standards and functional requirements.
- Architect, design, and implement (layered) self-checking environment using object-oriented strategies (with Vera) including behavioral functional models (BFM’s), traffic generators and checkers to cover block and/or full chip verification.
- Develop test-cases using random, permutated and directed tests to assure standards compliancy, feature coverage and achieve functional & code coverage goals.
- Debug of RTL design code, environments, models, test-cases, scripts and tools.
- Script development (using Perl, shell scripting, C/C++) to control tools and post-process results and logs.
- Participate in design reviews of architecture, RTL, and verification environments/plans.
- Contribute to post-silicon validation including: strategy; test-case generation; test equipment identification and usage; device bring-up, test and debug.

Qualifications

Minimum Experience Required:
- 8+ years experience in state-of-the-art ASIC/SoC design and verification methodologies using Verilog, Vera, System-Verilog, Specman and/or other equivalent object oriented programming languages
- Must demonstrate track record in test plan development and test case implementation. Also demonstrate experience in verification model development using verilog/vera hardware language
- Debug and bring-up the ASIC/FPGA in the lab. Must possess skills and aptitudes required to generate detailed schedules; make and meet commitments; facilitate teamwork and communication with local and multi-site and/or multi-discipline development teams

Preferred Experience:
- Ideal candidate will have experience in ASIC verification environment and test bench development for an entire chip that will apply to the Network/Communication market.
- Experience in passive optical network (PON) and switch router ASIC verification.
- Preferred skills include: C/C++, Tcl/Tk, Perl, Shell. VCS, Design Compiler, PrimeTime, Formality, NC Verilog, OrCAD. Ixia, Smartbit, Logic Analyzer, Oscilloscope, Cadence Palladium. UNIX, LINUX, Solaris operating systems.